1. Field
Embodiments of the invention relate to the field of microprocessors, and more specifically, to multiprocessor systems.
2. Background
A typical multiprocessor system has a number of processors running in parallel. By decomposing a large problem into smaller tasks and allowing these tasks to be executed by concurrent processors, a significant speed improvement is achieved. There are, however, many challenges facing multiprocessor design. Examples of these challenges include cache coherency, snooping protocol, task allocation, communication, and parallel compilers.
Current processors or microprocessors, having internal cache memories typically contains a tag memory that records the addresses of the cache lines accessed by the processor. The tags in the tag memory are compared against the address of a processor internal request. A match or a hit to a tag entry usually means the requesting data is contained in the processor cache. The data can be supplied directly from the cache instead of issuing an external cycle to fetch the data from the main memory. The tags are also compared to a cacheable cycle from another processor seen on the multiprocessor bus. A match to a tag entry requires the processor to take appropriate actions and signal the requesting processor of the ownership of the cache line. The monitoring of the multiprocessor bus by a processor is refer as “snooping”. The interactions between the requesting processor and snooping processor to ensure data consistency on the cache line is called “cache cohrency” as is well known. These interactions typically take up processor cycles. In addition, all cacheable agents have to complete the snoop activities before the cacheable cycle can complete. The snoop activities are often delayed because of slow tag timing or conflicts with on-going internal tag accesses.